This paper presents a novel CMOS low-power voltage limiter/regulator circuit with hysteresis for inductive power transfer in\nan implanted telemetry application. The circuit controls its rail voltage to the maximum value of 3V DC employing 100mV of\ncomparator hysteresis. It occupies a silicon area of only 127 ????m Ã?â?? 125 ????m using the 130 nm IBM CMOS process. In addition, the\ncircuit dissipated less than 1mW and was designed using thick-oxide 3.6V NMOS and PMOS devices available in the process\nlibrary.
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